ATmega128
The extreme values for the OCRnx Register represent special cases when generating a P W M
waveform output in the phase correct P W M mode. If the OCRnx is set equal to BOTTOM the
output will be continuously low and if set equal to TOP the output will be set to high for non-
inverted P W M mode. For inverted P W M the output will have the opposite logic values.
If OCRnA is used to define the TOP value ( W GMn3:0 = 9) and COMnA1:0 = 1, the OCnA Output
will toggle with a 50% duty cycle.
Timer/Counter
Timing Diagrams
The Timer/Counter is a synchronous design and the timer clock (clk Tn ) is therefore shown as a
clock enable signal in the following figures. The figures include information on when interrupt
flags are set, and when the OCRnx Register is updated with the OCRnx buffer value (only for
modes utilizing double buffering). Figure 55 shows a timing diagram for the setting of OCFnx.
Figure 55. Timer/Counter Timing Diagram, Setting of OCFnx, no Prescaling
clk I/O
clk Tn
(clk I/O /1)
TCNTn
OCRnx - 1
OCRnx
OCRnx + 1
OCRnx + 2
OCRnx
OCRnx Value
OCFnx
Figure 56 shows the same timing data, but with the prescaler enabled.
Figure 56. Timer/Counter Timing Diagram, Setting of OCFnx, with Prescaler (f clk_I/O /8)
clk I/O
clk Tn
(clk I/O /8)
TCNTn
OCRnx - 1
OCRnx
OCRnx + 1
OCRnx + 2
OCRnx
OCRnx Value
OCFnx
130
2467X–AVR–06/11
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